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ds04-28203-4e fujitsu semiconductor data sheet assp image processing bipolar a/d converter (1-channel, 8-bit low-power model with built-in clamp circuit) mb40568 n description the mb40568 is an all-parallel (flash type) a/d converter for 8-bit video applications, and uses high-speed bipolar process technology for low-power consumption and high-speed conversion. this a/d converter is capable of converting analog signals into digital signals at a rate of dc to 20 msps (megasamples per second). additional circuitry including a clamp circuit and reference voltage generator circuits are build in, to make the mb40568 ideally suited for video signal processing. n features ? resolution: 8 bits ? linearity error: 0.15 % typ. ? maximum conversion rate: 20 msps min. ? analog input voltage: 0 to 3 v in 2 v p-p (clamp circuit) 3 to 5 v (without clamp circuit) ? digital input/output level: ttl levels ? power supply voltage: +5 v single power supply ? power dissipation: 200 mw typ. n pac k ag e s 22-pin plastic sk-dip (dip-22p-m04) 24-pin plastic sop (fpt-24p-m02)
2 mb40568 n pin assignments n pin descriptions (continued) pin no. symbol function dip sop 1, 11 1, 11 d.gnd ground pin should be connected to the analog system ground. 2 to 9 2 to 9 d 8 to d 1 digital signal output pin 10 10 clk clock input pin 12, 22 12, 24 a.gnd ground pin should be connected to the analog system ground. 13, 21 13, 23 v ccd power supply voltage input pin also functions as v cca power supply, and should be in the same voltage level as v cca pin. 14, 20 14, 22 v cca power supply voltage input pin also functions as v ccd power supply, and should be in the same voltage level as v ccd pin. 15 15 v inc clamp circuit input pin the clamp circuit is a diode-clamp type sync chip clamp circuit. should be shorted to ground if the clamp circuit is not used. 16 16 v outc clamp circuit output pin a capacitor of at least 1 m f should be connected between this pin and the v clmp pin. should be left open if the clamp circuit is not used. d.gnd d 8 (lsb) d 7 d 6 d 5 d 4 d 3 d 2 d 1 (msb) clk d.gnd 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 a.gnd v ccd v cca v rb v ina v clmp v outc v inc v cca v ccd a.gnd (top view) (dip-22p-m04) (fpt-24p-m02) d.gnd d 8 (lsb) d 7 d 6 d 5 d 4 d 3 d 2 d 1 (msb) clk d.gnd a.gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a.gnd v ccd v cca v rb v ref v rm v ina v clmp v outc v inc v cca v ccd (top view)
3 mb40568 (continued) pin no. symbol function dip sop 17 17 v clmp clamp voltage output pin a capacitor of at least 1 m f should be connected between this pin and the v outc pin. should be left open if the clamp circuit is not used. 18 18 v ina analog signal input pin 19 v rb analog reference voltage pin in the dip model, this pin is internally connected to the reference circuit. always be sure that a capacitor is connected immediately next to the ic, between this pin and the ground. the capacitor must be at least 1 m f with excellent frequency characteristics. 19v rm reference voltage monitor pin set to the midpoint of resistance between v cca and v rb . should be left open in normal use. 20v ref reference voltage output pin should be left open when no reference voltage source is used. 21v rb analog reference voltage input pin when an internal reference voltage source is used, this pin should be shorted to the v ref pin. in this case, always be sure that a capacitor is connected immediately next to the ic, between this pin and the ground. the capacitor must be at least 1 m f with excellent frequency characteristics. when an external reference voltage source is used, this pin will carry a current of up to 8.5 ma, therefore it is necessary to use a voltage source with sufficient sync capacity. a capacitor connection should also be used similar to that used with internal reference voltage sources.
4 mb40568 n block diagrams 1. sk-dip clk v ina v cca r 1 r r/2 r/2 r r r 2 v rb 254 127 2 1 255 128 18 20 14 15 19 10 255 to 8 encoder latch & buffer 2 3 4 5 6 7 8 9 d 1 (msb) d 2 d 3 d 4 d 5 d 6 d 7 d 8 (lsb) r 16 17 11 1 22 12 21 13 v ccd v ccd d.gnd d.gnd a.gnd a.gnd v cca v inc v outc v clmp clamp circuit 0.6 v cc + 200 mv 0.6 v cc reference
5 mb40568 2. sop clk v ina v cca r 1 r r/2 r/2 r r r 2 v rb 254 127 2 1 255 128 18 22 14 15 21 10 255 to 8 encoder latch & buffer 2 3 4 5 6 7 8 9 d 1 (msb) d 2 d 3 d 4 d 5 d 6 d 7 d 8 (lsb) r 16 17 11 1 24 12 23 13 v ccd v ccd d.gnd d.gnd a.gnd a.gnd v cca v inc v outc v clmp clamp circuit 0.6 v cc + 200 mv 0.6 v cc reference 19 v rm 20 v ref 1
6 mb40568 n absolute maximum ratings (see warning) * : package : sop v cca = 2.0 0.1 v, v rb = 2.0 0.1 v warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions *1: v cca and v ccd must be used in the same voltage level. *2: package : sop v cca = 2.0 0.1 v, v rb = 2.0 0.1 v *3: v inc must have an amplitude of v cca C v clmp . parameter symbol rating unit power supply voltage v cca , v ccd C0.5 to +7.0 v digital input voltage v ind C0.5 to +7.0 v analog input voltage v ina C0.5 to v cc + 0.5 v analog reference voltage* v rb C0.5 to v cc + 0.5 v clamp circuit input voltage v inc C0.5 to v cc + 0.5 v storage temperature tstg C55 to +125 c parameter symbol value unit min. typ. max. power supply voltage* 1 v cca , v ccd 4.75 5.00 5.25 v analog input voltage v ina v rb v cca v analog reference voltage* 2 v rb 2.75 3 3.25 v clamp circuit input voltage* 3 v inc 03 v clamp capacitance c clmp 1 m f digital high-level output voltage i oh C400 m a digital low-level output voltage i ol 1.6ma clock pulse width at high-level t w + 22.5 ns clock pulse width at low-level t w C 22.5 ns operating temperature top 0 70 c
7 mb40568 n electric characteristics 1. dc characteristics (1) analog dc characteristics (v cca = v ccd = 4.75 to 5.25 v, ta = 0 c to +70 c) * : v cca = v ccd = 5.00 v, ta = +25c (2) digital dc characteristics (v cca = v ccd = 4.75 to 5.25 v, ta = 0 c to +70 c) * : v cca = v ccd = 5.00 v, ta = +25c parameter symbol value unit remarks min. typ. max. resolution 8 bits linearity error* le 0.15 0.3 % dc accuracy equivalent analog input resistance r ina 300 k w analog input capacitance c ina 4050pff ina = 1mhz analog high-level input current i iha 45 m av ina = v cca analog low-level input current i ila 40 m av ina = v rb clamp circuit input current i inc C600 C200 m av inc = 0 v reference voltage v rb 0.6 v cc C0.1 0.6 v cc 0.6 v cc +0.1 v sk-dip22p package v ref sop24p package short between v ref and v rb clamp voltage v clmp v rb + 0.2 v reference current i rb C8.5 C5.5 C3.0 ma sop24p package parameter symbol value unit remarks min. typ. max. digital high-level output voltage v oh 2.7 v i oh = C400 m a digital low-level output voltage v ol 0.4vi ol = 1.6 ma digital high-level input voltage v ihd 2.0 v digital low-level input voltage v ild 0.8v maximum input current i id 100 m av id = 7 v high-level input current i ihd 020 m av ihd = 2.7 v digital low-level input current i ild C100 C10 m av ild = 0.4 v power supply current i cc 40* 85 ma r ina = v cca C v rb i iha C i ila
8 mb40568 2. switching characteristics (v cca = v ccd = 4.75 to 5.25 v, ta = 0 c to +70 c) n timing diagram parameter symbol value unit min. typ. max. maximum conversion rate f s 20 msps digital output delay time t pd 81530ns 3 v 0 v v oh v ol clk v ina d 1 to d 8 sample n t w + t w 1.5 v data n ?1 t pd sample n + 2 sample n + 1 data n + 1 1.5 v data n
9 mb40568 n typical characteristic curves (continued) v cc = 5.25 v v cc = 5.00 v v cc = 4.75 v 100 80 60 40 20 10 ?5 0 25 50 75 100 power supply current vs. temperature power supply current i cc (ma) ambient temperature ta ( c) v cc = 5.00 v maximum conversion rate vs. temperature maximum conversion rate (mhz) 70 60 50 40 30 20 ?5 0 25 50 75 100 ambient temperature ta ( c) ?5 0 25 50 75 100 ambient temperature ta ( c) v ref ? rb short reference voltage vs. temperature 3.20 3.10 3.00 2.90 2.80 2.70 reference voltage v ref (v) v cc = 5.00 v v rb = 3.00 v 10 8 6 4 2 0 ?5 0 25 50 75 100 ambient temperature ta ( c) v cc = 5.00 v reference current vs. temperature reference current i rb (ma)
10 mb40568 (continued) (continued) ?5 0 25 50 75 100 ambient temperature ta ( c) 5.0 4.0 3.0 2.0 1.0 0 v cc = 4.75 v i oh = ?00 m a digital high-level output voltage v oh (v) digital low-level output voltage v ol (v) digital low-level output voltage vs. temperature ?5 0 25 50 75 100 ambient temperature ta ( c) v cc = 4.75 v i ol = 1.6 ma 0.5 0.4 0.3 0.2 0.1 0 digital high-level output voltage vs. temperature ?5 0 25 50 75 100 ambient temperature ta ( c) ?5 0 25 50 75 100 v cc = 5.00 v clamp voltage vs. temperature clamp voltage v clmp (v) 3.40 3.30 3.20 3.10 3.00 2.90 v cc = 5.00 v +le ?e linerity error vs. temperature linearity error le (%) 0.4 0.2 0 ?.2 ?.4 digital output delay time vs. power supply voltage digital output delay time t pd (ns) 4.50 4.75 5.0 5.25 5.50 50 40 30 20 10 0 power supply voltage v cc (v) t phl t plh clock pulse width vs. power supply voltage 4.50 4.75 5.0 5.25 5.50 power supply voltage v cc (v) 10 8 6 4 2 0 clock pulse width t w (ns) ta = +25 c t w t w + ambient temperature ta ( c)
11 mb40568 (continued) ?5 0 25 50 75 100 ambient temperature ta ( c) digital output delay time vs. temperature -25 0 25 50 75 100 ambient temperature ta ( c) v cc = 5.00 v digital output delay time t pd (ns) 50 40 30 20 10 0 v cc = 5.00 v t phl t plh clock pulse width vs. temperature clock pulse width t w (ns) 10 8 6 4 2 0 t w + t w 10 20 30 40 50 60 clock frequency (mhz) s/nq (rms signal/rms noise) vs. clock frequency s/nq (db) ta = +70 c ta = 0 c ta = +25 c v cc = 5.00 v f in = 4.0 mh z s/nq (rms signal/rms noise) vs. analog input frequency s/nq (db) analog input frequency (mhz) 50 40 30 20 10 0 0 2 4 6 8 10 v cc = 5.00 v f clk = 20 mhz ta = +25 c 50 40 30 20 10 0
12 mb40568 n equivalent circuit 1. analog input equivalent circuit 2. equivalent circuit of clamp circuit block v cca v ina 255 circuits a.gnd v cca v ina c ina a.gnd i bias v d r ina v rb c ina r ina v rb i bias v d : non-linear emitter-follower junction capacitance : linear resistance model for input current transition by comparator switching infinite value for v ina < v rb or when clk + high : voltage at v rb terminal. : constant input bias current : the base-collector junction diode of emitter-follower transistor v cca v inc a.gnd 2 ma 0.6 v cc + 200 mv + v be 850 k w v outc v clmp c clmp ?
13 mb40568 3. equivalent circuit of reference circuit block 4. digital input equivalent circuit 5. load circuit for output buffer v cca a.gnd 20 k w 30 k w v rb pin buffer i rb v ccd d.gnd v ref = 1.4 v 50 k w 6.5 k w 50 k w 3.2 k w 3.2 k w clock input to output pin measurement point c l d.gnd c l = 15 pf note: cl = 15 pf including scope and jig capacitance
14 mb40568 n linearity error 1. ideal conversion characteristics the values for v zt and v ft are typical values under conditions that v cca = v ccd = 5.000 v and v rb = 3.000 v. step 255 254 253 129 128 127 2 1 0 11111111 11111110 11111101 10000001 10000000 01111111 00000010 00000001 00000000 output code v zt 3.006 v v ft 4.996 v v ina
15 mb40568 2. actual conversion characteristics step 255 254 253 129 128 127 2 1 0 le128 le2 11111111 11111110 11111101 10000001 10000000 01111111 00000010 00000001 00000000 output code le253 le129 le127 le1 len max fs = linearity error v ft v ina v zt
16 mb40568 n clamp circuit operation the mb40568s internal clamp circuit is a peak-detection type circuit, which clamps compound synchronized signals using the lowest sync point as clamp voltage (v clmp ) (see illustration below). the clamp voltage is set at 0.6 v cc + 0.2 v (typical). if the clamp circuit is not used, the signal pins should be handled as follows: ?clamp circuit pin name description v inc connect to gnd v outc leave open v clmp leave open v cca v inc a.gnd 2 ma c clmp + v cca 15 16 17 18 video signal v outc v clmp v ina bias circuit 3.2 v a/d converter (pin no.: sk-dip22p) signal level at v inc pin a.gnd signal level at v ina pin v cca = 5.0 v v clmp 3.2 v v rb 3.0 v
17 mb40568 n typical connection examples 1. on-chip input pnp transistor utilized v inc + (pin no.: sk-dip22p) 15 16 17 18 video signal input +5 v +5 v v cca v ccd v outc v clmp v ina 1 m f a.gnd d.gnd mb40568
18 mb40568 2. input pnp transistor of clamp circuit is put externally + 15 16 17 18 +9 v +5 v +5 v external circuit video signal input (pin no.: sk-dip22p) 1 m f v cca v ccd v inc v outc v clmp v ina a.gnd d.gnd mb40568 2.2 k w 2sa933
19 mb40568 n ordering information part number package remarks mb40568p-sk 20 pin plastic sk-dip (dip-20p-m04) MB40568PF 24 pin plastic sop (fpt-24p-m02)
20 mb40568 n package dimensions (continued) 20-pin plastic sk-dip (dip-22p-m04) +.020 C0 +.008 C.012 C0 +.020 +0.50 C0 C0 +0.50 +0.20 C0.30 .050 3.00(.118)min 4.36(.172)max typ 7.62(.300) (.260.010) 6.600.25 1.070 .034 0.86 index-1 max 1.27(.050) 1.27 0.250.05 (.010.002) 0.51(.020)min 15max 27.18 typ 2.54(.100) index-2 (.018.003) 0.460.08 1994 fujitsu limited d22008s-4c-3 c dimensions in mm (inches)
21 mb40568 (continued) 24-pin plastic sop (fpt-24p-m02) +0.05 C0.02 +.002 C.001 +0.25 C0.20 +.010 C.008 (stand off) 0.05(.002)min 0.500.20(.020.008) (.362.012) 9.200.30 2.80(.110)max (.402.016) (.299.012) (.018.004) 0.450.10 10.200.40 7.600.30 13.97(.550)ref 1.27(.050)typ 1 pin index 0.15 .006 15.24 .600 details of "a" part 0.60(.024) 0.20(.008) 0.18(.007)max 0.68(.027)max "a" m ?0.13(.005) 0.10(.004) 1994 fujitsu limited f24008s-4c-4 c dimensions in mm (inches)
22 mb40568 memo
23 mb40568 memo
24 mb40568 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9702 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support. *ds04-2820 3

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